This invention relates to clock signal distribution circuitry for integrated circuit devices. Typically, the invention is embodied in clock signal distribution circuitry of structured application-specific integrated circuits (“structured ASICs”).
Structured ASICs are devices that have some predetermined circuit characteristics, but that are also customizable to some degree. For example, a structured ASIC may include a two-dimensional array of many relatively small logic elements (referred to herein as hard logic elements, hybrid logic elements, or HLES). The basic circuitry of these HLEs is always the same or substantially the same, and is provided by a subset of the masks that are used to make (fabricate) the structured ASIC. Accordingly, the masks in this subset can be always the same or substantially the same. The overall function(s) performed by an HLE can be customized to some extent by customizing one or more additional masks used to make a particular structured ASIC product. Similarly, connections to, from, and/or between HLEs can be customized by customizing additional masks used to make the product. Because the structured ASIC always has the same basic circuitry, the task of designing it to perform particular tasks is greatly simplified, speeded up, increased in reliability, and reduced in cost. An entire ASIC does not have to be designed “from scratch.” Instead, only the customizable masks have to be designed.
A possible use of structured ASIC technology is to produce ASICs that are functionally equivalent to programmed field-programmable gate arrays (“FPGAs”). After a logic design has been adequately “proven” in an FPGA, the design may be “migrated” to a structured ASIC implementation. References such as Chua et al. U.S. Pat. No. 7,243,329 and Schleicher et al. U.S. Pat. No. 7,275,232 show this type of use of structured ASIC technology.
FPGAs typically include a “core” of many instances of programmable logic blocks (and possibly also other blocks such as memory, digital signal processing or DSP circuitry, etc.) in a highly regular pattern (e.g., a two-dimensional array of intersecting rows and columns of circuit blocks). FPGAs also typically include many instances of input/output or IO circuitry, which may be arranged in a ring around the outside or periphery of the device (and therefore around the above-mentioned core circuitry). Both the core circuitry and the above-mentioned IO or peripheral circuitry are very often intensive and extensive users of clock signals. For example, the core circuitry may include many data signal registers that need to be clocked at precise times to reliably store and subsequently output data signals applied to them. The peripheral IO circuitry also typically includes many instances of data signal registers that need to be precisely clocked for similar purposes.
An FPGA may need to distribute many different clock signals in parallel to many different parts of the circuitry. For example, these different clock signals may have different phase shifts relative to one another, and/or they may have different frequencies relative to one another (e.g., as a result of dividing the frequency of one signal by several different frequency division factors to produce several derivative clock signals). Some of these clock signals may need to be made available throughout all or at least a large portion of the FPGA. Other clock signals may only be needed in certain relatively confined areas on the FPGA.
To meet all of these various possible clock signal needs, an FPGA is typically given clock signal distribution circuitry that is both extensive and highly flexible in terms of its usability (i.e., by being programmable or configurable to route any of many different clock signals in many different ways from various possible sources to various possible destinations). Nevertheless, there are typically some significant limitations on how clock signals can be routed in an FPGA. For example, IO registers associated with a particular row or column of core logic blocks in an FPGA may only be able to receive significantly fewer than all the clock signals on the FPGA, and also significantly fewer clock signals than the number of IO registers that are associated with that row or column. As a specific example, an FPGA may have a total of 26 different clock signals theoretically available to the IO registers associated with a core column, and it may have 24 IO registers associated with that column. But the clock signal routing may be such that only 9 different clock signals can actually reach those 24 registers.
As mentioned above, FPGAs typically have a highly regular core structure (e.g., a two-dimensional array of intersecting rows and columns of logic blocks). The above-mentioned clock circuitry on an FPGA can have a well-defined arrangement relative to this well-defined pattern of logic blocks. On the other hand, structured ASICs of the type shown in the above-mentioned Chua et al. and Schleicher et al. references have a different core architecture in which there is no predetermined correspondence, for example, between the functions performed in a particular FPGA core column or row and equivalent functions performed in any particular portion of the structured ASIC core circuitry. This can make it more difficult, in a structured ASIC implementation that is intended to be functionally equivalent to a programmed FPGA, to get the clock signals that are needed by particular peripheral IO registers to those registers. Moreover, some users may want pin-for-pin compatibility between the IO pins of the functionally equivalent FPGA and structured ASIC, while other users may want the pin-outs of these two, otherwise functionally equivalent devices to be different (so-called non-socket migration). Considerations such as these militate against “structuring” the peripheral clock distribution circuitry of a structured ASIC. On the other hand, leaving such circuitry completely or highly unstructured is contrary to the benefits that are typically sought through the use of structured ASICs (e.g., quick, reliable, and low-cost conversion of a programmed FPGA design into a structured ASIC implementation).